With the development of the semiconductor technology, fin field effect transistors (FETs) represent new CMOS devices for improving FET performance. The gate of a conventional planar transistor is located over the channel on one side, while the gate of a FinFET surrounds the channel from two sides, thus electrostatic control may be implemented for the channel from two sides. By such design, the FinFET can improve the control over the channel, reduce short-channel effect, and reduce the gate length effectively. However, compared to the embedded silicon germanium (e-SiGe) PMOS process for increasing the carrier mobility of the PMOS device, it is much more difficult to form stressors in source/drain region of a p-type FinFET since the conventional method may cause the deformation of the FinFET structure and the nonuniformity of the stressors in source/drain region.
To be specific, a conventional method of forming stressors, such as SiGe, in source/drain region of a p-type FinFET comprises the following steps: coating a photoresist layer on the FinFET structures; removing the photoresist on the p-type FinFET by exposure and development; etching and epitaxially growing SiGe in the p-type FinFET source/drain region. Although simple, such method may lead to the structural deformation of the FinFET. Moreover, in the known method, the SiGe does not grow uniformly by epitaxial growth and the scope of the embedded SiGe is difficult to control.